In memory devices in general including NAND flash memories, metal wires (bit lines) of the size near a resolution limit of lithography are used in a memory device part. Bit lines in a memory device part are mainly formed by a line & space pattern such that the wire width and the width of a dielectric film are in a one-to-one relation. By using such a one-to-one line & space pattern, a periodically repeated pattern is formed so that lithographic resolution is improved and still finer wire patterns can be formed. In the memory device part, a layout in which a wire called a shunt line is arranged in parallel may be adopted in the one-to-one line & space pattern. The shunt line is a wire used for charging and discharging source lines of a plurality of transistors in the memory device part, and a lower-layer contact plug and an upper-layer contact plug are connected to the shunt line. The shunt line is connected to source lines of the plurality of transistors via the lower-layer contact plug and to a control circuit via the upper-layer contact plug. Since the upper-layer contact plug connected to the shunt line is formed simultaneously with a contact plug used in a peripheral circuit part in the same layer, the diameter thereof becomes larger than that of the bit line. Therefore, the shunt line has been formed with a wire width equal to or thicker than that of the upper-layer contact plug. In this way, the upper-layer contact plug is prevented from being disconnected from the shunt line by making the wire width thicker.
However, if the shunt line is made thicker, periodicity of lithography breaks down, making arrangement of a thick-width shunt line immediately adjacent to a plurality of fine bit lines difficult. Thus, steps such as exercising control to improve periodicity by providing a space between bit lines and a shunt line or maintaining periodicity by arranging an auxiliary pattern on a photo mask have been necessary. However, if a space is provided between bit lines and a shunt line, there is a problem that a chip area increases by an area corresponding to the space. Further, even if such steps are taken, it is currently impossible to completely remove deterioration in contrast of fine wires by a shunt line and deterioration in lithographic resolution. Further, a pattern of several fine wires by a shunt line is more likely to break and thus, such wires cannot be used as bit lines. Therefore, these wires had to be made dummy wires not allowed to operate as a device. Then, if such dummy wires are provided, there is a problem that the chip area increases for the dummy wires.
With higher integration and higher performance in recent years, there is a trend to replace aluminum (Al) alloys conventionally used as a wire material with copper (Cu) or Cu alloys (hereinafter, called Cu together) having lower resistance in the memory device part to achieve high-speed performance of LSI. On the other hand, aluminum (Al) or tungsten (W) is used for the lower-layer contact plug and upper-layer contact plug connected to a shunt line. Here, particularly if Al is used as the plug material, Cu and Al cause an alloy reaction when the Al contact plug and a Cu wire are brought into contact. Therefore, it is necessary to arrange a barrier metal film between the Al contact plug and a Cu wire.
Here, a technology in which a thick-width wire portion to be a sense amplifier in a device portion of a memory array region is formed as two tungsten wires and a connection wire extending over the two tungsten wires is connected to a connector plug to be a communicating path to other wiring layers that fills a through hole formed in a gap portion between the two tungsten wires is disclosed (see Published Unexamined Japanese Patent Application No. 2005-19784, for example). However, this is a technology concerning a sense amplifier connected to bit lines and does not solve problems when a thick-width shunt line is arranged in parallel between a plurality of bit lines.